Source code for scalesim.memory.read_port

# Dummy memory like interface to service the requests of the last level memory

[docs] class read_port: """ Class to define dummy memory like interface to service the requests of the last level memory """ def __init__(self): """ The constructor method for the class """ self.latency = 1
[docs] def set_params(self, latency): """ Method to set the backing buffer hit latency for housekeeping. :param latency: Hit latency of the backing buffer :return: None """ self.latency = latency
[docs] def get_latency(self): """ Method to get the backing buffer hit latency for housekeeping. :return: Hit latency of the backing buffer """ return self.latency
# The incoming read requests will be needed when the capability of port is expanded # At the moment its kept for compatibility
[docs] def service_reads(self, incoming_requests_arr_np, incoming_cycles_arr): """ Method to service read request by the read buffer. As a dummy memory, everything is a hit :param incoming_requests_arr_np: matrix containg address of the memory requsts made from systolic array :param incoming_cycles_arr: list containg cycles at which the memory requsts are made from systolic array :return: List of out cycles by adding the hit latency to the incoming cycles """ out_cycles_arr = incoming_cycles_arr + self.latency return out_cycles_arr